1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and in particular, to a semiconductor device having a field-effect transistor and a method of manufacturing the same.
2. Description of the Background Art
In recent years, semiconductor devices typically including an SRAM (Static Random Access Memory) and a DRAM (Dynamic Random Access Memory) have been highly integrated to have such a structure that each chip includes many elements. Among these elements, a majority of transistors are field-effect transistors called MOSFETs (Metal Oxide Semiconductor Field Effect Transistors).
The MOSFETs can be classified into two types having different electric polarities, i.e., an nMOSFET (negative MOSFET) in which electrons flow through a channel region and a pMOSFET (positive MOSFET) in which holes flows. These nMOSPETs and pMOSPETs are combined to form various kinds of circuits.
Structures of such transistors can be roughly classified into a surface channel type and a buried channel type. Generally in the CMOS structure which consists of an MOSFET and a pMOSFET on the same substrate, the nMOSFET of the surface channel type and the pMOSFET of the buried channel type are broadly employed because it is necessary to use the same gate electrode material for the nMOSFET and pMOSFET. Structures of the conventional nMOSFET and pMOSFET will be described below.
FIG. 40 is a schematic cross section showing a structure of a conventional nMOSFET. Referring to FIG. 40, a silicon substrate 501 is provided at its surface with a boron diffusion region 503 of p-type. A pair of n-type source/drain regions 507 are formed at the surface of boron diffusion region 503 with a predetermined space between each other. A gate electrode 511 is formed at a region located between paired source/drain regions 507 with a gate insulating film 509 therebetween.
Paired n-type source/drain regions 507, gate insulating film 509 and gate electrode 511 form an nMOSFET 520 of surface channel type.
Side walls of gate electrode 511 are covered with side wall spacer 513.
FIG. 41 is a cross section schematically showing a structure of a conventional pMOSFET. Referring to FIG. 41, a silicon substrate 601 is provided at its surface with a phosphorus diffusion region 603 of n-type. A pair of p-type source/drain regions 607 are formed at the surface of phosphorus diffusion region 603 with a predetermined spaced between each other. A gate electrode 611 is formed at a region located between paired source/drain regions 607 with a gate insulating film 609 therebetween. A p-type buried channel region 615 is formed at the surface of phosphorus diffusion region 603 located between paired source/drain regions 607.
Paired p-type source/drain regions 607, gate insulating film 609, gate electrode 611 and p-type buried channel region 615 form a pMOSFET 620 of buried channel type.
Side walls of gate electrode 611 are covered with side wall spacer 613.
A method of manufacturing the conventional nMOSFET shown in FIG. 40 will be described below.
FIGS. 42 to 46 are schematic cross sections showing the process of manufacturing the conventional nMOSFET in accordance with the order of process steps. Referring first to FIG. 42, the ordinary LOCOS (Local Oxidation of Silicon) is executed to form isolating oxide films 521 on silicon substrate 501. In this step, isolating implantation regions 523 under isolating oxide films 521 are formed. Thereafter, a pad oxide film 531 of a predetermined thickness is formed to cover the whole surface.
Referring to FIG. 43, boron (B) is implanted into the whole surface. Then, a heat processing is executed to activate and diffuse the implanted boron, so that boron diffusion region 503 is formed at the surface of silicon substrate 501. Thereafter, pad oxide film 531 is removed, e.g., by etching.
Thereby, the surface of boron diffusion region 503 is exposed as shown in FIG. 44.
Referring to FIG. 45, thermal oxidation is effected, so that a silicon oxide film 509a as the gate insulating film is formed on the whole surface.
Referring to FIG. 46, patterned gate electrode 511 is formed on the surface of gate insulating film 509a. Using gate electrode 511 as a mask, ion implantation or the like is performed to form at the surface paired n-type source/drain regions 507 spaced by a predetermined distance. Then, side wall spacer 513 are formed to cover the side walls of gate electrode 511.
(a) As transistors are miniaturized to a higher extent, a concentration of impurity generally increases in accordance with a scaling rule. In accordance with this, the impurity concentration at the channel region increases in MOSFET 520 shown in FIG. 40, and thus inversion of the surface of channel region is suppressed. This results in increase of a threshold voltage of MOSFET 520 of surface channel type.
(b) If the impurity concentration at the channel region increases in MOSFET 520, carriers moving in the channel scatter to a higher extent. Therefore, mobility of minority carriers at the channel decreases, so that improvement of the drive performance of transistor cannot be substantially expected.
(c) In the pMOSFET 620 of buried channel type shown in FIG. 41, buried channel region 615 is of p-type having the same polarity as source/drain regions 607, and makes connection between paired p-type source/drain regions 607. By controlling gate applied voltage, the degree of depletion in buried channel region 615 can be changed for modulating the current flowing through the channel.
However, the depletion layer width formed by the gate electric field is smaller than 50 nm from the substrate surface. Further, the depletion layer at the p-n junction between buried channel region 615 and phosphorus diffusion region 603 expands for only about 50 nm or less toward buried channel region 615. Therefore, the depth of buried channel region 615 must be smaller than about 100 nm in order to deplete whole buried channel region 615 by the gate voltage.
In general, p-type buried channel region 615 is formed by implantation of boron. Since boron has a small mass and a large diffusion coefficient, it is difficult to form a shallow buried diffusion region, and its depth from the substrate surface exceeds 100 nm due to a heat treatment at a later step. When the depth of buried channel region 615 from the substrate surface exceeds 100 nm, a non-depleted region is formed at buried channel region 615 even if a voltage is applied to gate electrode 611. In this case, a current which cannot be controlled by gate electrode 611, i.e., so-called punch-through current is generated.
(d) In pMOSFET 620, source/drain regions 607 are formed by implantation of boron. As already described, boron has a strong tendency to diffuse. Therefore, it is difficult to suppress diffusion of boron from source/drain regions 607 toward the channel region. Accordingly, a effective channel length decreases, which makes it difficult to miniaturize the transistor structure.
For the above reasons (a)-(d), it is difficult to miniaturize the conventional MOSFET.
An object of the invention is to provide a transistor structure which can be miniaturized without difficulty.
Another object of the invention is to improve a drive performance of a transistor while allowing miniaturization of a transistor structure.
Yet another object of the invention is to suppress generation of a punch-through current during operation of a transistor even in the case where a transistor structure is miniaturized.
According to one aspect of the invention, a semiconductor device having a field-effect transistor includes a semiconductor substrate, a pair of source/drain regions, a gate electrode, and a nitrogen introduced region. The semiconductor substrate is of a first conductivity type, and has a main surface. The paired source/drain regions are of a second conductivity type, and are formed at the main surface of the semiconductor substrate with a predetermined space between each other. The gate electrode is opposed to a region located between the paired source/drain regions and is formed on the main surface of the semiconductor substrate with a gate insulating film therebetween. The nitrogen introduced region is formed at a region of the semiconductor substrate located between the paired source/drain regions, contains nitrogen, and has a concentration peak of the nitrogen. The concentration peak of the nitrogen extends from the main surface of the semiconductor substrate to a position at a depth not exceeding 500 xc3x85.
According to another aspect of the invention, a semiconductor device having a field-effect transistor includes a semiconductor substrate, a pair of source/drain regions, a gate electrode, and a nitrogen introduced region. The semiconductor substrate is of a first conductivity type, and has a main surface. The paired source/drain regions are of a second conductivity type, and are formed at the main surface of the semiconductor substrate with a predetermined space between each other. The gate electrode is opposed to a region located between the paired source/drain regions and is formed on the main surface of the semiconductor substrate with a gate insulating film therebetween. The nitrogen introduced region is formed at a region of the semiconductor substrate located between the paired source/drain regions, contains nitrogen, and has a peak concentration of the nitrogen. The peak concentration of the nitrogen is located at the main surface of the semiconductor substrate.
According to the semiconductor device of the former aspect of the invention described above, the nitrogen introduced region has the peak concentration of the nitrogen extending from the main surface of the semiconductor substrate to the position at the depth not exceeding 500 xc3x85. According to the semiconductor device of the latter aspect of the invention described above, the nitrogen introduced region has the peak concentration of the nitrogen located at the main surface of the semiconductor substrate. Thus, in the semiconductor devices according to these two aspects, the nitrogen introduced region is located at the channel region of the field-effect transistor. The nitrogen can serve to suppress diffusion of boron. Therefore, the boron outside the channel region is prevented from diffusing into the channel region, so that increase of a threshold voltage of a transistor in an nMOSFET is suppressed, and a drive performance of the transistor can be improved. Meanwhile, in a pMOSFET, the source/drain regions formed by implantation of boron are prevented from extending toward the channel region, so that a long effective channel length can be ensured. Since the boron in the channel region is prevented from diffusing into a region outside the channel region, the buried channel region in the buried type pMOSFET is prevented from extending unnecessarily deeply from the substrate surface, and generation of a punch-through current is suppressed. For the above reasons, the transistor structure can be miniaturized without difficulty.
According to the semiconductor device of a preferred aspect of the invention, the semiconductor substrate has a p-type region containing boron introduced thereinto, and the paired source/drain regions are of an n-type conductivity type.
According to the semiconductor device of the above aspect of the invention, the boron introduced into semiconductor substrate tends to diffuse toward the channel region, e.g., due to heat treatment at a later step. However, the channel region has the nitrogen introduced region, so that diffusion of boron into the channel region is prevented. Therefore, the boron concentration can be low at the channel region, so that an inversion layer can be easily formed at the channel region. Accordingly, the threshold voltage of the transistor can be set low.
Since the boron concentration can be low at the channel region, impurity scattering of electrons flowing through the channel can be suppressed to a considerable extent. This improves the current drive performance of the transistor.
Further, it is possible to increase the boron concentration at a position deeper than the channel region from the substrate surface, while maintaining the low boron concentration at the channel region. Therefore, punch-through at a deep portion of the substrate can be prevented, and a punch-through breakdown voltage can be improved.
According to still another preferred aspect of the invention, the semiconductor device further includes a buried channel region of n-type formed at a region of the semiconductor substrate located between the paired source/drain regions. A p-n junction formed by the n-type buried channel region and the p-type region in the semiconductor substrate containing the boron introduced thereinto is located within the nitrogen introduced region.
According to the semiconductor device of the above preferred aspect, the boron in the substrate tends to diffuse from a deep position in the substrate toward the buried channel region, e.g., due to a heat treatment at a later step. However, diffusion of the boron introduced into the substrate toward the channel region is prevented owing to provision of the nitrogen introduced region at the channel region. Therefore, at the vicinity of the p-n junction formed by the boron introduced into the substrate and the buried channel region, a large concentration gradient in the buried channel region is maintained. Therefore, a large potential in the direction of depth can be ensured at the buried region, and a wide channel region can be ensured. Accordingly, the drive performance of the transistor can be improved.
Further, it is possible to increase the boron concentration at a position deeper than the channel region from the substrate surface, while preventing diffusion of boron introduced into the substrate toward the channel region. Therefore, punch-through at a deep portion of the substrate can be prevented, and a punch-through breakdown voltage can be improved.
According to the semiconductor device of further another preferred aspect of the invention, the semiconductor substrate has an n-type region, and the paired source/drain regions have a p-type region containing boron introduced thereinto.
According to the semiconductor device of the above aspect of the invention, the boron in the source/drain regions tends to diffuse toward the channel region due to, e.g., a heat treatment at a later step. However, the channel region is provided with the nitrogen introduced region, so that diffusion of boron in the source/drain regions into the channel region is prevented. Therefore, extension of the source/drain regions toward the channel region is prevented, so that a large effective channel length can be ensured.
The semiconductor device of further preferred aspect of the invention further includes a buried channel region of p-type formed by introduction of boron into the main surface of the semiconductor substrate located between the paired source/drain regions. A p-n junction formed by the p-type buried channel region and the n-type region in the semiconductor substrate is located within the nitrogen introduced region.
According to the semiconductor device of the above aspect of the invention, the boron in the buried channel region tends to diffuse from a portion near the substrate surface toward a deep portion due to, e.g., a heat treatment at a later step. However, the channel region is provided with the nitrogen introduced region, so that the boron in the channel region is prevented from diffusing into the deep portion of the substrate. Therefore, the buried channel region can be shallow, and the buried channel region can be entirely controlled by a gate voltage to form a depletion layer, so that generation of a punch-through current is suppressed.
A method of manufacturing a semiconductor device having a field-effect transistor according to one aspect of the invention includes the following steps.
First, a pair of source/drain regions of a second conductivity type is formed at a main surface of a semiconductor substrate of a first conductivity type with a predetermined space between each other. A gate electrode opposed to a region located between the paired source/drain regions is formed on the main surface of the semiconductor substrate with a gate insulating film therebetween. A nitrogen introduced region having a peak concentration of the nitrogen extending to a position at a depth not exceeding 500 xc3x85 from the surface of the semiconductor substrate is formed at a region of the semiconductor substrate located between the paired source/drain regions.
The above manufacturing method can manufacture the semiconductor substrate according to the aforementioned one aspect of the invention having the effects described before.
A method of manufacturing a semiconductor device having a field-effect transistor according to another aspect of the invention includes the following steps.
First, a pair of source/drain regions of a second conductivity type is formed at a main surface of a semiconductor substrate of a first conductivity type with a predetermined space between each other. A gate electrode opposed to a region located between the paired source/drain regions is formed on the main surface of the semiconductor substrate with a gate insulating film therebetween. A nitrogen introduced region having a peak concentration of the nitrogen located at the main surface of the semiconductor substrate is formed at a region of the semiconductor substrate located between the paired source/drain regions.
The above manufacturing method can manufacture the semiconductor substrate according to aforementioned another aspect of the invention having the effects described before.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.